In this article, we proposed a newly designed multiplier with low power consumption and high speed in processes based on a new structure. Due to increasing demand for integrated circuits with being higher in speed, lower in delays, higher in power efficiency as well as more compact in size, we decided to design a new structure to enhance the mentioned characteristics. It is common to use adder units in designing digital multiplier cells and here it has been used the same method. In our proposed structure has been utilized of 4×4-bit adder units since it is the base structure in digital multipliers. The main merits of this multiplier are the least adder unit count, ultra-low power consumption, and propagation delay in comparison with other structures. Here, some of the most prevalent multiplier structures such as Array multiplier, RCA multiplier, Braun multiplier, Bypassing RCA, Bypassing CSA have been simulated in HSPICE software by using 28T full adder cell; At the next stage, a comparison among them and hence our proposed multiplier has been applied. As it can be figured out from the comparison results, the proposed structure enjoys the best performance in terms of power consumption, propagation delay, throughput and latency compared to the other simulated structures. The figures demonstrates that the proposed structure consumes 25% less power than Bypassing RCA multiplier (the lowest power consumer among the rest of mentioned structures) , moreover, its propagation delay and adder units count are respectively 36.15% and 16.7% lower than Bypassing RCA multiplier. Note that all of these simulations have been carried out by HSPICE in 0.18 m technology at 1.8V supply voltage. To make a long story short, our proposed design is the best choice to fit in low power and high speed arithmetic applications.
کلید واژگان :ropagation Delay, RCA Multiplier, Braun Multiplier, Bypassing RCA, and Bypassing CSA
ارزش ریالی : 600000 ریال
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